Implementation of Software Defined Radio

Implementation of Software Defined Radio

The evolution of the mobile technology happens every day. While first cellphones designed were restricted to making calls and barely sending messages, current mobile devices are capable of streaming media across the globe in speed never considered before.

The progress made in this area is recorded in a timeline, divided by generations:

- The 2G smartphones were capable of sending and receiving data at very slow rates of transmission.

- When the 3G mobile technology was released, the speed and reliability of transmission was significantly increased but it was still no perfect. They were too dependent of the antennas and physical conditions, like location and weather.

- The 4th Generation consists in improvements of the 3G, but there is still a long way to go.

For a mobile device to use a specific network, such as GSM, 2G, 3G and so on, it is necessary to implement network protocols. These protocols define the network that will be provided to the user, so it is very important to accomplish their standards to achieve quality required by the users. Their implementations, however, are not simple or flexible: for each one of them, it is demanded to have a hardware, which can be complicated and may require more resources.

To help solve this issue, the Software Defined Radio concept can implement the protocols in software instead of hardware. The benefits would be the enhancing of flexibility and the reduction of time needed to switch between one standard to another.

The design of the SDR project consists in converting physical layer functions into software. To do such improvement, the processes of treating, modulating and transmitting the signal would no longer be part of a hardware application. The one device that can be used to perform the SDR functions is FPGA (Field Programmable Gate Array), but first the code must be designed.

For this specific project, the SDR was divided in blocks of implementation, each one to be worked on and developed separately. They were programmed on Matlab, so that in a future work they would be translated to Simulink and then to IP core, so that the implementation on the FPGA can be possible.

While the modulation chosen is Quadrature Phase Shift Keying (QPSK), so that the signal is less dependent of the power spectrum, the blocks developed in this project are:

- Scrambler/Descrambler

These two blocks have opposite logics. The scrambler randomizes the input sequence of bits so that the interferences with adjacent channels are minimized. The reason this happens is because of the power of the signal is dispersed along the spectrum. It user a Linear Feedback Shift Register (LFSR) that stores the bits and performs logical operations (XOR) with them, avoiding long sequences of zeros and ones.

- Hamming Encoder/ Decoder

They detect and correct errors. The detection can be up to 2 bits while the correction is of 1 bit. The Hamming Encoder uses a parity bit check in its logic, which add specific bits that will be used in future calculations to find corruptions in the sequence.

- Interleaver/ De-interleaver

With the goal of protecting the sequence from burst errors, the interleaver divides the input in symbols (blocks of two bits) and rearrange the sequence using two Random Access Memories (RAMs) to do such task.

- Constellation Mapper/ Constellation De-mapper

Using the mentioned QPSK technique, symbols are created and plotted according to coordinates of imaginary and real parts of complex numbers, which are the multiplication between the bits and the phase of the QPSK.

The goal of this project is to enhance the communication of the transmitter and receiver, considering advents from the channel, like noise. After projecting and programming the blocks individually, they were linked and adapted to work as one code so that simulations could be performed. The next steps would be modulating the signal to simulate a transmission and testing the improvement each block offers to the system. Also, the translation of the code to Simulink and then to the FPGA would be a physical result of the work done during the weeks of the research.